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| TS3404 Single Synchronous Buck PWM Controller Pin assignment 1. Boot 8. Phase 2. Ugate 7. COMP 3. Gnd 6. FB 4. Lgate 5. Vcc Oscillator Frequency up to 300KHz 0.8V Internal Reference Drives N-Channel MOSFETs General Description The TS3405 makes simple work out of implementing a complete control and protection scheme for a DC-DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, the TS3405 integrates the control, output a adjustment, monitoring and protection functions. The TS3405 provides simple, single feedback loop, voltage mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 8V/uS slew rate, which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. The protection from over current conditions is provided by monitoring the Rds(on) of the lower MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. Features Buck converter Vin operate from 3.3V ~ 14V Vcc operate from 3.75V ~ 6V Buck converter Vin can be greater than Vcc 0.8V to Vin output voltage 1.5% over line voltage and temperature Simple single -loop control design Voltage-mode PWM control Loss less, programmable over current protection uses lower MOSFET's Rds(on) Internal soft start Converter can source and sink current Fixed oscillator frequency 300KHz Applications Power supplies for microprocessors Subsystem power supplies Cable modems, set-top box, DSL modems DSP and core communications processor supplies Memory supplies Personal computer peripherals Industrial power supplies Low-voltage distributed power supplies Ordering Information Part No. TS3405CS Operating Temp. -40 ~ +85 C o Package SOP-8 Absolute Maximum Rating Supply Voltage Operating Supply Voltage Absolute Boot Voltage Upper Driver Supply Voltage Input, Output or I/O Voltage Operating Junction Temperature Range Ambient Temperature Range Storage Temperature Range Lead Temperature 1.6mm(1/16") from case for 10Sec. TJ TJ TSTG TLEAD VCC VCC VBOOT VBOOT VPHASE 6 4.5 ~ 5.5 20 20 Gnd-0.3V to Vcc+0.3V -40 ~ +125 -40 ~ +85 -65 ~ +150 260 V V V V V o o o o C C C C TS3405 1-10 2003/12 rev. A Pin Descriptions No. 1 Pin. Boot Descriptions This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-lever N-channel MOSFET. It can take 20V as the maximum voltage. It can be powered by a DC power supply or powered by a boost strap circuit. This pin provides the PWM controlled gate driver for the upper MOSFET. It is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET can be turned on. The sourcing Rds(on) is 15 and the sink Rds(on) is 7. Ugate can handle high voltage up to maximum 20V. This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. This pin provides the PWM controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET can be turned on. This pin provides the bias supply for the TS3405, as well as the lower MOSFET's gate. Connect a well-decoupled 5V supply to this pin. This pin is the inverting input of the internal error amplifier. Use this pin in combination with the COMP Pin to compensate the voltage-control feedback loop of the converter. During soft start and all the time during normal converter operation, this pin represents the output of the error amplifier. Use this pin in combination with the FB pin to compensate the voltage control feedback loop of the converter. Pulling COMP to a level below 0.3V enables soft start process. The whole soft start process takes about 5mS. This pin is used to monitor the voltage drop across the lower MOSFET for over current protection. The OCP threshold is -30mV. If Phases is less thean -300mV, the upper MOSFET cannot be turned-on in the next cycle. 2 Ugate 3 4 Gnd Lgate 5 6 7 Vcc FB COMP 8 Phase Block Diagram TS3405 2-10 2003/12 rev. A Electrical Characteristics (Iout= 0mA, and Tj = +25 oC; unless otherwise specified.) Parameter Vcc supply current Nominal supply Power-on reset Rising Vcc power-on reset threshold Vcc power-on reset threshold Hysteresis Oscillator Frequency Ramp amplitude Reference Reference voltage Tolerance Nominal reference voltage Error Amplifier DC Gain Gain-bandwidth product Slew rate Gate Drivers Upper gate source driver Upper gate sink driver Lower gate source driver Lower gate sink driver Protection / Disable OCP threshold Disable threshold VOCP VDISABLE VVCC= 5V, sweep Phase Sweep COMP ---300 0.3 --mV V IUGATE-SRC IUGATE-SNK ILGATE-SRC ILGATE-SNK VVCC= 5V, ILGATE = 100mA VBOOT= 10V, IUGATE = 100mA ----15 7 9.5 3.5 ---- GBWP SR COMP= 10pF -14 4.65 82 -8.0 --9.2 dB MHz V/uS VREF ---0.8 1.5 -% V FOSC VOSC Vcc= 5V 250 -300 1.5 340 -KHz V POR 3.8 0.24 4.0 0.25 4.2 0.30 V IVcc 2.6 -3.8 mA Symbol Test Conditions Min Typ Max Unit Typical Application Vcc_5V Rfilter Cbulk Dboot CHF U1 CDCPL Vcc Boot Vgate Phase Gnd Lgate TS3405 COMP Q1 Cboot Lout Q2 Vout Cout RF C1 CF FB RS Roffset Single Power 5V Application TS3405 3-10 2003/12 rev. A Typical Application (continued) Vcc_5V Rfilter Dboot Cbulk CHF Vcc_12V U1 CDCPL Vcc Boot Vgate Phase Gnd Lgate Q2 Cboot TS3405 RF C1 CF COMP FB Q1 Lout Vout Cout RS Roffset Single Power 5V and 12V Application Vin Rfilter Cbulk Dboot CHF U1 Vcc CDCPL Boot Vgate Phase Gnd Lgate RC1 Q2 RC2 Q1 Cboot Lout Cout Vout TS3405 RF C1 CF COMP FB RS Roffset Adjustable OCP Point Application TS3405 4-10 2003/12 rev. A Typical Application (continued) H3 Vin_Gun H1 Vcc R5 33 C13 C14 D1 1N4148 C5A C5B TP1 BNC C13 10uF/16V(MLCC Vcc Roset 20K_5% C4 105 U1 Boot TS3405 Vgate COMP Gnd Q1 C6 L1 104 1.6uH/30A H2 Vout C8 C9 JP1 2 R2 43K_1% FB Phase Lgate 1 Jumper C1 821 C2 222 R4 1.5K_1% Q2 C10 H4 Vout_Gun R1 3.3K_1% C3 223 R3 56_1% Component MOSFET Inductor No. of input capacitor No. of output capacitor No. of decoupling capacitor Reference design Q1B Q2 L1 C13B C14 C8B C9B C10 C5AB C5B Maximum load current 5A Rds(on)O 30m 5uF 1 1 1 10A Rds(on)O 20m 3uF 1 2 1 15A Rds(on)O 10m 1.6uF 2 3 2 Reference design capacitor G 1500uF(ESR=33) Reference design decoupling capacitor G 10uF(MLCC) TS3405 5-10 2003/12 rev. A Functional Description Start Up The TS3405 automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the Vcc pin. The POR function initiates the Soft Start (SS) operation after the supply voltage exceeds its POR threshold. Over Current Protection (OCP) The over current function protects the converter from a shorted output by using the lower MOSFET's on-resistance, Rds(on), to monitor the current. Therefore, even the power input voltage is greater than Vcc, TS3405 still can support this. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The TS3405's OCP threshold is a fixed value, -300mV, when Phase voltage is less -300mV, the next on-cycle will not be initialized. Over Voltage Protection (OVP) An over voltage protection comparator is monitoring the COMP. When COMP voltage is less than 0.3V, the Soft Start (SS) process is initiated. Soft Start (SS) Both POR and OVP initiate the soft start sequence after the over current set point has been sampled. Soft Start clamps virtually the error amplifier output (COMP pin) and reference input (non-inverting terminal of the error amp) to the internally generated Soft Start voltage. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates Phase pulses of increasing width that charge the output capacitor(s). when the internally generated Soft Start voltage exceeds the COMP pin voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically takes about 5mS. Current Sinking The TS3405 incorporates a MOSFET shoot-through protection method which allows a converter to sink current as well as source current. Care should be exercised when designing a converter with the TS3405 when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the buck converter input power, if the buck converter input power has the same supply source which supplies the bias voltage, Vcc to the TS3405. if there is nowhere for this current to go, such as to other distributed loads on the Vcc rail, through a voltage limiting protection device, or other methods, the capacitance on the Vcc bus will absorb the current. This situation will allow voltage level of the Vcc rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the TS3405, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode. TS3405 6-10 2003/12 rev. A Application Guidelines Component Selection Input Capacitor Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turn on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high side MOSFET (Q1) and the source of low side MOSFET (Q2). The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current rating above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. MOSFET The TS3405 requires 2 N-channel power MOSFETs. These should be selected based upon Rds(on), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the equations below). These equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the upper and lower MOSFET's body diode. The gate-charge losses are dissipated by the TS3405 and do not heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating tempature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Losses while sourcing current: 2 PUPPER= Io x Rds(on) x D + 1/2 Io x Vin x tSW x FS PLOWER= Io2 x Rds(on) x (1- D) Losses while sinking current: 2 PUPPER= Io x Rds(on) x D PLOWER= Io2 x Rds(on) x (1-D) + 1/2 Io x Vin x tSW x FS Where: D is the duty cycle = Vout / Vin tSW is the combined switch ON and OFF time FS is the switching frequency Given the reduced available gate bias voltage (5V), logic-level or sub-logic-level transistors should be used for both N-MOSFETs. Caution should be exercised with devices exhibiting very low Vgs(on) characteristics. The shoot through protection present aboard the TS3405 may be circumvented by there MOSFETs if they have large parasitic impedances and /or capacitances that would inhibit the gate of the MOSFET from being discharged below it's threshold level before the complementary MOSFET is turned on. +5V Dboot + VD _ Boot Cboot -5V CHF Vcc Vgate Q1 TS3405 Phase Lgate _ + Gng Q2 FIGURE 5B Upper Gate drive bootstrap. Fig. 5 shows the upper gate drive (Boot pin) supplied by a bootstrap circuit from Vcc. The boot capacitor. CBOOT, develops a floating supply voltage referenced to the Phase pin. The supply is refreshed to a voltage of Vcc less the boot diode drop (VDP) each time the lower MOSFET turns on. TS3405 7-10 2003/12 rev. A Application Guidelines (continued) Output Inductor The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: I = (Vin - Vout) / FS x L x (Vout / Vin) Vout = I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the TS3405 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor to minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: tRISE = (L x ITRAN) / (Vin - Vout) tFALL = (L x ITRAN) / Vout where: ITRAN is the transient load current step tRISE is the response time to the application of load tFALL is the response time to the removal of load the worst case response time can be either at the equations at the minimum and maximum output levels for the worst case response time. Feedback Compensation Fig. 6 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (Vout) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with a amplitude of Vin at the Phase node. The PWM wave is smoothed by the output filter (Lo and Co). The modulator transfer function is the small-signal transfer function of Vout / VE/A. This function is dominated by a DC Gain and the output filter (Lo and Co), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the imput voltage (Vin) divided by the peak-to-peak oscillator voltage VOSC. Modulator Break Frequency Equations FLC = 1 / 2 x Lo x Co FESR = 1 / 2 x ESR x Co Compensation Break Frequency Equations FZ = 1 / 2 x R2 x C1 FP1 = 1 / 2 x R2 x [(C1 x C2) / (C1 + C2)] FZ1 = 1 / 2 x (R1 + R3) x C3 FP2 = 1 / 2 x R3 x C3 The compensation network consists of the error amplifier (internal to the TS3405) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. Vin Driver Lout Vout OSC OSC PWM _ + Driver Phase Co ESR ZIN + Reference Error AMP DETAILED COMPENSATION COMPONENT ZFD VE/A _ C2 ZFD Vout C1 R2 COMP C3 R3 R1 _ + FB ZIN TS3405 Reference FIGURE 6B Voltage-mode buck converter compensation design. TS3405 8-10 2003/12 rev. A Application Guidelines (continued) The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2 and C3) in Fig. 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. st 2. Place 1 zero below filter's double pole (~75% FLC) nd 3. Place 2 zero at filter's double pole. st 4. Place 1 pole at the ESR zero. nd 5. Place 2 pole at half the switching frequency 6. Check gain against error amplifier's open-loop gain. 7. Estimate phase margin - repeat if necessary. Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/nS. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent Series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Feedback Divider The reference of TS3405 is 0.8V. the output voltage can be set by R1 and R4 as shown in Fig. 4. The equation is following: Vout = 0.8 x (1 + R1 / R4) The R1 should be between 2k to 5k. put the R1, R4 and others compensation component as close to TS3405 as possible. Shutdown Pulling low the COMP pin can shutdown the TS3405 PWM controller. You can use a small single transistor as switch like as JP1 shown in Fig. 4. Compensation Break Frequency Equations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. Using wide, short printed circuit traces should minimize these interconnecting impedances. The critical components should be located as close together as possible, using ground plane construction or single point grounding. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. Locate the TS3405 within 3 inches of the MOSFETs. Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the TS3405 must be sized to handle up to 1A peak current. Provide local Vcc decoupling between Vcc and Gnd pins. Locate the capacitor, CBOOT as close as practical to the Boot and Phase pins. All components used for feedback compensation should be located as close to the IC a practical. TS3405 9-10 2003/12 rev. A SOP-8 Mechanical Drawing A DIM SOP-8 DIMENSION MILLIMETERS INCHES MIN MAX MIN MAX 4.80 5.00 0.189 0.196 3.80 4.00 0.150 0.157 1.35 1.75 0.054 0.068 0.35 0.49 0.014 0.019 0.40 1.25 0.016 0.049 1.27 (typ) 0.05 (typ) 0.10 0.25 0.004 0.009 0o 7o 0o 7o 5.80 6.20 0.229 0.244 0.25 0.50 0.010 0.019 16 9 B P 1 8 G C D K M R F A B C D F G K M P R TS3405 10-10 2003/12 rev. A |
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